Graphene and Carbon Nanotubes (CNT) are candidates for replacing silicon in high and medium performance logic devices. One factor affecting the performance of these devices is the contact resistance arising at the metal-CNT/Graphene interface. This resistance is the main contributor of mobility degradation in short channel devices. Several solutions have been suggested to overcome this problem, such as using a high work function metal, which can lower the schottky barrier at the metal-p-type nanotube interface, thereby decreasing the resistance at the contacts.
However, such an approach depends heavily on the work function of the material being probed, which in the case of CNTs varies with tube diameter. For example, in the absence of a suitable high work function metal, it is difficult to make satisfactory contacts onto small diameter CNTs.
Another existing approach to reduce the barrier at the contacts is to increase the electron density at the interface. This thins down the tunnel barrier present at the interface due to increase in electrical band bending, helping a direct tunneling of the electron into the CNT. Typically, such an effect is achieved using an external gate field in a field-effect transistor (FET) type structure. However, effect of gate on the contacts may vary this depending upon FET device geometry due to the change in electrostatics of the system. Also, gate fields are not able to penetrate near the metal-CNT/graphene contacts due to shielding by contact metals. This is particularly the case where metal is beneath the CNT/graphene channel (bottom contacted devices).
Accordingly, there is a need for reducing contact resistance for contacts to CNT/graphene.